programmable delay generation on Xilinx FPGA

Xilinx FPGA-based implementation of the parameterized delay line with good resolution, say in steps of 10ps and good delay range say 512 steps and with minimum FPGA resources say less than 2% utilization.

Deliverables

1. RTL code in Verilog/SV/VHDL and Xilinx Syntheis scripts
2. TB and Verification environment (with parameters) and results
3. Documentation with Architecture Diagram, Algorithm with Flow chart etc