analog model in system verilog or UVM
Less than a week- Basic Level
- Expired
Project detail
Have a few equations which need to be implemented in system Verilog or uvm. It will have sine functions, signed numbers, etc. Have a reference model in VHDL
Less than a week
Basic Level
ExpiredHave a few equations which need to be implemented in system Verilog or uvm. It will have sine functions, signed numbers, etc. Have a reference model in VHDL