VHDL expert required for computer architecture

Implement the single-cycle MIPS CPU, as explained in Section A.9 and the figure in the below,
that supports add, sub, and or, slt, lw, sw, beq, and j instructions on the DE10-Lite FPGA board
using VHDL hardware description language and Quartus FPGA design software.

Section A.9 and figure i will share later